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[AK4141] rev. 0.3-pb 2008/01 - 1 - general description the AK4141 is a nicam/a2/eia-j st ereo decoder, which is optimized fo r digital tv application. the AK4141 achieves no alignment, few external com ponents and high audio performance by digital stereo decoding architecture. the AK4141 int egrates a stereo sample rate c onverter (src) for asynchronous digital audio sources such as hdmi, digital tuner, digi tal switches and sound proce ssing functions such as 5-band equalizers. the AK4141 supports major audi o data formats (msb/lsb justified, i 2 s and tdm) to interface with dsp, adc, dac. t herefore, the AK4141 is suitable for t he av systems such as digital tv and dvr. features 1. stereo decoding ? capable of receiving sound intermedia te frequency (sif) with selector and fm demodulation ? automatic gain control (agc: 100mvpp ~ 1vpp) for sif input ? alignment free digital stereo decoding eia-j nicam: b/g, l, i, d/k with fm/am mono a2: b/g, d/k1, d/k2, d/k3, m/n ? automatic/manual stereo d ecoding standard selection ? automatic/manual audio mode (s tereo/mono/two sounds) selection ? signal quality detection for auto selection mode ? high fm deviation option (max: 540khz) ? i2s sampling rate (fs): 32k/44.1k/48khz 2. audio processing (two stereos) ? automatic level control (alc) ? balance ? 5-band equalizer ? stereo separation emphasis ? digital volume control with soft mute (+12db~-115db, 0.5db/step) ? audio data interface: i2s input x 5 (2 inputs: src available) i2s output x 3 master/slave mode audio format: 24bit left justif ied /right justified / i 2 s or tdm 3. asynchronous sample rate converter (src) ? input sample rate: 8k~192khz ? fso/fsi: 1/6~6 4. digital audio interface transmitter (dit) with through mode 5. integrated x?tal oscillator 6. master clock: 256fs/384fs/512fs/768fs/1024fs 7. i2c-bus control interface 8. power supply: 1.8v0.1v, 3.3v0.3v 9. ta: -20 ~ 85 c 10. package: 48pin lqfp nicam/a2/eia-j digital stereo decoder AK4141 = preliminary =
[AK4141] rev. 0.3-pb 2008/01 - 2 - mclki sif1 lrck sclk x?tal osc pll clock gen gnd5 avdd2 pdn fm demod & stereo decode eiaj nicam a2 switch matrix control register scl sda int vrefl adc (sif) dit xti xto txin txout sdti1 sdti2 sdti3 sdto1 sdto2 sdto3 a lc, vol1 balance1 bass/tre1 3d agc a lc, vol2 balance2 bass/tre2 3d src lrck4 sclk4 sdti4 sif2 decoder prescale src prescale prescale 1/2/3/4 lrck 5 sclk5 sdti5 gnd2 vrefh cad0 cad1 6m5 4m50 4m51 4m52 mcko msn iis gnd1 dvdd tvdd lflt2 lflt1 vcom gnd3 avdd1 gnd4
[AK4141] rev. 0.3-pb 2008/01 - 3 - ordering guide AK4141eq -20 +85 c 48pin lqfp (0.5mm pitch) akd4141 evaluation board for AK4141 pin layout 37 gnd4 36 38 vrefh 39 sif2 40 vcom 41 sif1 42 43 vrefl 44 avdd1 45 xto 46 gnd5 47 35 34 33 32 31 sclk 30 mclko 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 23 22 21 20 19 18 17 16 15 14 13 dvdd mclki pdn txin gnd1 scl a 4m51 AK4141eq top view gnd3 48 12 24 25 xti gnd2 tvdd a 4m52 sdto2 sdto3 a6m5 int cad1 cad0 lrck sdto1 msn lflt1 avdd2 sda sdti4 lflt2 sclk5 sdti5 lrck4 iis sclk4 sdti2 sdti1 lrck5 sdti3 a4m50 txout
[AK4141] rev. 0.3-pb 2008/01 - 4 - pin/function no. pin name i/o function 1 filt2 o pll loop filter 2 pin a 0.68 f capacitor should be connected to gnd5 externally. hi-z when pdn pin = ?l?. 2 iis i audio data format select pin. ored with odif bit, ored with idif0 bit. ?l?: 24bit left justified if idif0 bit = ?0?(default) ?h?: 24/16 bit iis 3 lrck5 i input channel clock 5 pin 4 sclk5 i audio serial data clock 5 pin 5 sdti5 i audio serial data input 5 pin 6 lrck4 i input channel clock 4 pin 7 sclk4 i audio serial data clock 4 pin 8 sdti4 i audio serial data input 4 pin should be synchronized to lrck and sclk when src is not used. 9 sdti3 i audio serial data input 3 pin 10 sdti2 i audio serial data input 2 pin 11 sdti1 i audio serial data input 1 pin 12 a4m50 i decoder standard preference control 0 pin for 4.5mhz carrier this pin is internally xored with a4m50 bit (default = ?1?). 13 a4m51 i decoder standard preference control 1 pin for 4.5mhz carrier this pin is internally xored with a4m51 bit (default = ?1?). 14 scl i control data clock pin for i2c bus 15 pdn i power-down mode & reset pin when ?l?, the AK4141 is powered-down, all registers are reset. and then all digital output pins go ?l?. the AK4141 must be reset once upon power-up. 16 mcki i master clock input pin 17 txin i s/pdif input pin for through output. no input amplifier integrated. 18 dvdd - digital power supply pin, 1.7v~1.9v 19 gnd1 - ground pin, 0v 20 gnd2 - ground pin, 0v 21 tvdd - i/o buffer power supply pin, 1.7v~3.6v 22 sda i/o control data pin for i2c bus 23 a4m52 i decoder standard preference control 2 pin for 4.5mhz carrier this pin is internally ored with a4m52 bit (default = ?0?). 24 txout o s/pdif output pin. ou tputs ?l? when pdn pin = ?l?. 25 mcko o master clock output pin. outputs ?l? when pdn pin = ?l?. 26 sclk i/o audio serial data clock pin. outputs ?l? when pdn pin = ?l? and msn pin = ?h?. hi-z when pdn pin = ?l? and msn pin = ?l?. 27 lrck i/o input channel clock pin outputs ?l? when pdn pin = ?l? and msn pin = ?h?. hi-z when pdn pin = ?l? and msn pin = ?l?. 28 sdto3 o audio serial data output 3 pin outputs ?l? when pdn pin = ?l?. 29 sdto2 o audio serial data output 2 pin outputs ?l? when pdn pin = ?l?. 30 sdto1 o audio serial data output 1 pin outputs ?l? when pdn pin = ?l?.
[AK4141] rev. 0.3-pb 2008/01 - 5 - pin/function 31 int o interrupt pin outputs ?l? when pdn pin = ?l?. 32 a6m5 i decoder standard preference control for 6.5mhz carrier. ?l?: secam l nicam ?h?: d/k1, d/k2, d/k3 or d/k nicam this pin is internally ored with a6m5 bit (default = ?0?). 33 msn i master mode select pin ?l?: slave mode if cks[2:0] bits = ?000?(default) ?h?: master mode of mclk = 256fs if cks2 bit = ?0?(default) 34 cad0 i chip address 0 pin should match cad0 bit in i2c first byte. 35 cad1 i chip address 1 pin should match cad1 bit in i2c first byte. 36 filt1 o pll loop filter 1 pin a 4.7nf capacitor should be connected to gnd3 externally. hi-z when pdn pin = ?l?. 37 vrefh o adc voltage reference high pin a 0.1 f capacitor should be connected to gnd3, and another 0.1 f capacitor should be connected to vrefl pin externally. hi-z when pdn pin = ?l?. 38 vrefl o adc voltage reference low pin a 0.1 f capacitor should be connected to gnd3 externally. hi-z when pdn pin = ?l?. 39 gnd3 - ground pin, 0v 40 sif2 i sound intermediate frequency(sif) input 2 pin 41 vcom o adc common voltage output pin. a 1 f capacitor should be connected to gnd3 externally. hi-z when pdn pin = ?l?. 42 sif1 i sound intermediate frequency(sif) input 1 pin 43 avdd1 - analog power supply pin, 3.0v~3.6v 44 gnd4 - ground pin, 0v 45 xti i x'tal input pin 46 xto o x'tal output pin. outputs ?l? when pdn pin = ?l?. 47 gnd5 - ground pin, 0v 48 avdd2 - analog power supply pin, 3.0v~3.6v note: all digital input pins should not be left floating.
[AK4141] rev. 0.3-pb 2008/01 - 6 - handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog sif1, sif2 these pins should be connected to gnd through 10nf capacitor. txout, mclko, sdto1, sdto2, sdto3, int, lrck(master mode), sclk(master mode) these pins should be open. digital lrck5, sclk5, sdti5, lrck4, sclk4, sdti4, lrck(slave mode), sclk(slave mode), sdti3, sdti2, sdti1, a4m50, a4m51, a4m52, a6m5, scl, mclki, txin, sda, iis, msn, cad1, cad0 these pins should be connected to gnd. absolute maximum ratings (gnd1=gnd2=gnd3=gnd4=gnd5=0v; note 1 ) parameter symbol min max units power supplies analog digital digital i/o avdd dvdd tvdd -0.3 -0.3 -0.3 4.3 2.4 4.3 v v v input current, any pin except supply iin - 10 ma analog input voltage (sif1, sif2 pin) vina ? 0.3 avdd+0.3 v digital input voltage ( note 2 ) vind ? 0.3 tvdd+0.3 v ambient temperature (powered applied) ta ? 20 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. lrck5, sclk5, sdti5, lrck4, sclk4, sdti4, lrck(slave mode), sclk(slave mode), sdti3, sdti2, sdti1, a4m50, a4m51, a4m52, a6m5, scl, mclk i, txin, sda, iis, msn, cad1 and cad0 pin. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (gnd1=gnd2=gnd3=gnd4=gnd5=0v; note 1 ) parameter symbol min typ max units power supplies avdd dvdd tvdd avdd dvdd tvdd 3.0 1.7 dvdd 3.3 1.8 3.3 3.6 1.9 3.6 v v v warning: akemd assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4141] rev. 0.3-pb 2008/01 - 7 - audio characteristics (ta=25 c; avdd=3.3v, dvdd=1.8v, tvdd=3.3v; gnd1 =gnd2=gnd3=gnd4=gnd5=0v; fs=48khz; sclk=64fs; signal frequency=1khz; 24bit data; measurement frequency=50hz 13khz; unless otherwise specified) sif & demodulator parameter min typ max units sif input impedance gsel bit = 0 gsel bit = 1 4.05 5.09 4.50 5.66 kohm kohm sif separation ( note 3 ) 40 db agc step width 0.64 db input voltage 1 or 2 fm carriers gsel bit = ?0? gsel bit = ?1? 1 fm and 1 nicam carrier gsel bit = ?0? gsel bit = ?1? 1 am and 1 nicam carrier gsel bit = ?0? gsel bit = ?1? 1 nicam only gsel bit = ?0? gsel bit = ?1? 0.1 0.1 0.1 0.1 0.1 0.1 0.05 0.05 1.4 1.0 1.4 1.0 0.8 0.8 1.0 1.0 vpp vpp vpp vpp vpp vpp vpp vpp max fm-deviation (approx.) normal high deviation very high deviation +/-180 +/-360 +/-540 khz khz khz nicam characteristics min typ max units output level (1khz, 0dbr) -1.5 +1.5 db s/n 74 80 db thd+n 0.05 0.15 % nicam bit error rate (fm+ nicam, normal condition) 1 10 -7 frequency response (20 ~ 15khz, -12db, dual) -1 +1 db nicam crosstalk attenuation (dual) 80 db channel separation (stereo) 80 db fm characteristics ( note 4) min typ max units output level (1khz, 0dbr) -1.5 +1.5 db s/n 67 73 db thd+n 0.1 0.3 % frequency response (20 ~ 12khz, -12db, dual) -1 +1 db fm crosstalk attenuation (dual) 75 85 db channel separation (stereo) 30 40 db am characteristics min typ max units s/n 47 62 db thd+n 1.2 3 % frequency response (20 ~ 12khz, -12db, dual) -2.5 +1 db note 3. selected sif pin is connected to gnd through 10nf capacitor. note 4. 1 fm-carrier, 5.5mhz.
[AK4141] rev. 0.3-pb 2008/01 - 8 - audio characteristics (continued) (ta=25 c; avdd=3.3v, dvdd=1.8v, tvdd=3.3v; gnd1 =gnd2=gnd3=gnd4=gnd5=0v; fs=48khz; sclk=64fs; signal frequency=1khz; 24bit data; measurement frequency=50hz 13khz; unless otherwise specified) eiaj characteristics min typ max units s/n stereo sub 54 54 60 60 db db thd+n (1khz l or r or sub 100%) stereo sub 0.3 0.3 0.9 0.9 % % frequency response stereo (20 ~ 12khz, 100%eim) sub (20 ~ 12khz, 100%eim) -1 -1 +1 +1 db db channel separation (stereo) 30 40 db src characteristics (ta=25 c; avdd=3.3v, dvdd=1.8v, tvdd=3.3v; gnd1 =gnd2=gnd3=gnd4=gnd5=0v; fs=48khz; sclk=64fs; signal frequency=1khz; 24bit data; measurem ent frequency=20hz ~ fso/2; unless otherwise specified) parameter symbol min typ max units src characteristics: resolution 20 bits input sample rate fsi 8 216 khz output sample rate fso 32 48 khz thd+n (input = 1khz, 0dbfs, note 5 ) fso/fsi = 48khz/8khz fso/fsi = 48khz/32khz fso/fsi = 48khz/192khz worst case (fso/fsi = 32khz/176.4khz) - - - - -100 -100 -100 - - - - tbd db db db db dynamic range (input = 1khz, ? 60dbfs, a-weighted, note 5 ) fso/fsi = 48khz/8khz fso/fsi = 48khz/32khz fso/fsi = 48khz/192khz worst case (fso/fsi = 48khz/32khz) - - - tbd 103 103 103 - - - - - db db db db ratio between input and output sample rate fso/fsi 1/6 6 - note 5. measured by audio precision system two cascade. power supplies parameter min typ max units power supply current normal operation (pdn pin = ?h?) tvdd avdd1+avdd2 dvdd power-down mode (pdn pin = ?l?; note: 1 ) tvdd avdd1+avdd2 dvdd 5 20 70 10 10 10 tbd tbd tbd 100 100 100 ma ma ma a a a note: 1. all digital inputs including clock pins are held at dvdd or gnd.
[AK4141] rev. 0.3-pb 2008/01 - 9 - src filter characteristics (ta=25 c; avdd=3.0 3.6v, dvdd=1.7v 1.9v, tvdd=1.7 3.6v; gnd1=gnd2=gnd3=gnd4=gnd5=0v) parameter symbol min typ max units digital filter 0.985 fso/fsi 6.000 pb 0 0.4583fsi khz 0.905 fso/fsi < 0.985 pb 0 0.4167fsi khz 0.714 fso/fsi < 0.905 pb 0 0.3195fsi khz 0.656 fso/fsi < 0.714 pb 0 0.2852fsi khz 0.536 fso/fsi < 0.656 pb 0 0.2182fsi khz 0.492 fso/fsi < 0.536 pb 0 0.2177fsi khz 0.452 fso/fsi < 0.492 pb 0 0.1948fsi khz 0.357 fso/fsi < 0.452 pb 0 0.1458fsi khz 0.324 fso/fsi < 0.357 pb 0 0.1302fsi khz 0.246 fso/fsi < 0.324 pb 0 0.0917fsi khz 0.226 fso/fsi < 0.246 pb 0 0.0826fsi khz passband ? 0.01db 0.1667 fso/fsi < 0.226 pb 0 0.0583fsi khz 0.985 fso/fsi 6.000 sb 0.5417fsi khz 0.905 fso/fsi < 0.985 sb 0.5021fsi khz 0.714 fso/fsi < 0.905 sb 0.3965fsi khz 0.656 fso/fsi < 0.714 sb 0.3643fsi khz 0.536 fso/fsi < 0.656 sb 0.2974fsi khz 0.492 fso/fsi < 0.536 sb 0.2813fsi khz 0.452 fso/fsi < 0.492 sb 0.2604fsi khz 0.357 fso/fsi < 0.452 sb 0.2116fsi khz 0.324 fso/fsi < 0.357 sb 0.1969fsi khz 0.246 fso/fsi < 0.324 sb 0.1573fsi khz 0.226 fso/fsi < 0.246 sb 0.1471fsi khz stopband 0.1667 fso/fsi < 0.226 sb 0.1020fsi khz passband ripple pr 0.01 db 0.985 fso/fsi 6.000 sa 102.2 db 0.905 fso/fsi < 0.985 sa 100.4 db 0.714 fso/fsi < 0.905 sa 99.0 db 0.656 fso/fsi < 0.714 sa 101.6 db 0.536 fso/fsi < 0.656 sa 99.5 db 0.492 fso/fsi < 0.536 sa 95.2 db 0.452 fso/fsi < 0.492 sa 96.6 db 0.357 fso/fsi < 0.452 sa 97.0 db 0.324 fso/fsi < 0.357 sa 94.4 db 0.246 fso/fsi < 0.324 sa 95.8 db 0.226 fso/fsi < 0.246 sa 95.0 db stopband attenuation 0.1667 fso/fsi < 0.226 sa 73.7 db group delay ( note 6 ) gd - 56 - 1/fs note 6. this value is the time from the rising edge of lrck after data is input to rising edge of lrck after data is output, when lrck for output data corresponds with lrck for input.
[AK4141] rev. 0.3-pb 2008/01 - 10 - dc characteristics (ta=25 c; avdd=3.0 3.6v, dvdd=1.7v 1.9v, tvdd=1.7 3.6v; gnd1=gnd2=gnd3=gnd4=gnd5=0v) parameter symbol min typ max units high-level input voltage tvdd < 2.7v tvdd 2.7v low-level input voltage tvdd < 2.7v tvdd 2.7v vih vih vil vil 80%tvdd 70%tvdd - - - - - - - - 20%tvdd 30%tvdd v v v v high-level output voltage ( iout=-400 a) low-level output voltage (iout= -400 a(except sda pin), 3ma(sda pin)) voh vol tvdd-0.4 - - - 0.4 v v input leakage current iin - - 10 a switching characteristics (ta=-20 85 c; avdd= 3.0~3.6v, dvdd=1.7~1.9v tvdd= 1.7~3.6v; gnd1=gnd2=gnd3=gnd4=gnd5=0v; c l =20pf, cb=400pf(sda pin)) parameter symbol min typ max units crystal resonator frequency fs=32khz fs=44.1khz fs=48khz fxtal 256fs 8.192 11.2896 12.288 mhz mhz mhz master clock timing master clock 128fs: pulse width low pulse width high 192fs: pulse width low pulse width high 256fs: pulse width low pulse width high 384fs: pulse width low pulse width high 512fs: pulse width low pulse width high 768fs: pulse width low pulse width high 1024fs: pulse width low pulse width high fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 4.096 65 65 6.144 43 43 8.192 27 27 12.288 20 20 16.384 16 16 24.576 11 11 32.768 8 8 6.144 9.216 12.288 18.432 24.576 36.864 49.152 mhz ns ns mhz ns ns mhz ns ns mhz ns ns mhz ns ns mhz ns ns mhz ns ns
[AK4141] rev. 0.3-pb 2008/01 - 11 - switching characteristics (continued) (ta=-20 85 c; avdd= 3.0~3.6v, dvdd=1.7~1.9v tvdd= 1.7~3.6v; gnd1=gnd2=gnd3=gnd4=gnd5=0v; c l =20pf, cb=400pf(sda pin)) parameter ( note 8 ) symbol min typ max units lrck timing (slave mode) normal mode (tdm=?0?) lrck frequency duty cycle fs duty 32 45 48 55 khz % tdm256 mode (tdm=?1?) lrck frequency ?h? time ?l? time fs tlrh tlrl 32 1/256fs 1/256fs 48 khz ns ns src input lrck frequency duty cycle fs duty 8 45 192 55 khz % lrck timing (master mode) normal mode (tdm=?0?) lrck frequency duty cycle fs duty 32 50 48 khz % tdm256 mode (tdm=?1?) lrck frequency ?h? time ( note 7) fs tlrh 32 1/8fs 48 khz ns audio interface timing (slave mode) normal mode (tdm=?0?) sclk period sclk pulse width low pulse width high lrck edge to sclk ? ? ( note 9 ) sclk ? ? to lrck edge ( note 9 ) lrck to sdto(msb) (except i 2 s mode) sclk ? ? to sdto sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 160 65 65 30 30 10 10 35 35 ns ns ns ns ns ns ns ns ns tdm256 mode (tdm=?1?) sclk period sclk pulse width low pulse width high lrck edge to sclk ? ? ( note 9 ) sclk ? ? to lrck edge ( note 9 ) sclk ? ? to sdto tdmin hold time tdmin setup time tbck tbckl tbckh tlrb tblr tbsd tsdh tsds 81 32 32 20 20 10 10 20 ns ns ns ns ns ns ns ns src input ( note 10 ) sclk period sclk pulse width low pulse width high lrck edge to sclk ? ? ( note 9 ) sclk ? ? to lrck edge ( note 9 ) sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tsdh tsds 81 32 32 20 20 10 10 ns ns ns ns ns ns ns
[AK4141] rev. 0.3-pb 2008/01 - 12 - switching characteristics (continued) (ta=-20 85 c; avdd= 3.0~3.6v, dvdd=1.7~1.9v tvdd= 1.7~3.6v; gnd1=gnd2=gnd3=gnd4=gnd5=0v; c l =20pf, cb=400pf(sda pin)) parameter ( note 8 ) symbol min typ max units audio interface timing (master mode) normal mode (tdm=?0?) sclk frequency sclk duty sclk ? ? to lrck sclk ? ? to sdto fbck dbck tmblr tbsd ? 20 ? 40 64fs 50 20 40 hz % ns ns tdm256 mode (tdm=?1?) sclk frequency sclk duty ( note 11 ) sclk ? ? to lrck sclk ? ? to sdto tdmin hold time tdmin setup time fbck dbck tmblr tbsd tsdh tsds ? 12 ? 20 10 10 256fs 50 12 20 hz % ns ns ns ns power-down & reset timing pdn pulse width ( note 12 ) pdn ? ? to sdto valid ( note 13 ) tpd tpdv 150 tbd ns 1/fs note 7. ?l? time at i 2 s format. note 8. sclk= sclk/sclk4/sclk5, lrck= sclk/lrck4/lrck5 unless otherwise specified. note 9. sclk rising edge must not occur at the same time as lrck edge. note 10. sclk= sclk4/sclk5, lrck= lrck4/lrck5. note 11. this value is mclk=512fs. duty cycle is not guaranteed when mclk=256fs/384fs. note 12. the AK4141 can be reset by bringing the pdn pin = ?l?. note 13. this cycle is the number of lrck rising edges from the pdn pin = ?h?. parameter symbol min typ max units control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling ( note 14 ) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter capacitive load on bus fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp cb - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 0 400 - - - - - 0.9 - 0.3 0.3 - 50 400 khz s s s s s s s s s s ns pf note 14. data must be held for sufficient tim e to bridge the 300 ns transition time of scl. note 15. i 2 c is a registered trademark of philips semiconductors.
[AK4141] rev. 0.3-pb 2008/01 - 13 - timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fs lrck vih vil tbck tbckl vih tbckh sclk vil figure 1. clock timing (tdm bit = ?0?) 1/fclk tclkl vih tclkh mclk vil 1/fs lrck vih vil tlrl tlrh tbck tbckl vih tbckh sclk vil figure 2. clock timing (tdm bit = ?1?)
[AK4141] rev. 0.3-pb 2008/01 - 14 - lrck vih vil tblr sclk vih vil tlrs sdto 50%tvdd tlrb tbsd figure 3. audio interface timing (slave mode, normal mode) tlrb lrck vih sclk vil sdto 50%tvdd tbsd vih vil tblr tsds sdti vih vil tsdh figure 4. audio interface timi ng (slave mode, tdm mode)
[AK4141] rev. 0.3-pb 2008/01 - 15 - lrck sclk sdto tbsd tmblr 50%tvdd 50%tvdd 50%tvdd sdti tdxh tdxs vih vil figure 5. audio interface timing (master mode, normal mode) lrck sclk sdto 50%tvdd tbsd tmblr tsds tdmin vih vil tsdh 50%tvdd 50%tvdd figure 6. audio interface timi ng (master mode, tdm mode) tpd pdn vil pdn vih vil tpdv sdto 50%vdd figure 7. power down & reset timing
[AK4141] rev. 0.3-pb 2008/01 - 16 - thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp figure 8. i 2 c bus mode timing
[AK4141] rev. 0.3-pb 2008/01 - 17 - package 1 12 48 13 7.0 9.0 0.2 7. 0 9.0 0.2 0.22 0.1 48pin lqfp(unit:mm) 0.10 37 24 2 5 36 1.40 0.05 0.13 0.13 1.70max 0 10 0.10 m 0.3~0.75 0.5 package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatmen t: solder (pb free) plate
[AK4141] rev. 0.3-pb 2008/01 - 18 - marking AK4141eq xxxxxxx 1 xxxxxxx: date code identifier important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.
[AK4141] rev. 0.3-pb 2008/01 - 19 - thank you for your access to akemd products information. more detail product information is available, please contact our sales office or authorized distributors.

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